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[Other] wave0001

Description: 在MAX-PLUS下设计的函数消耗发生器，波形有正弦波、方波、三角拨、锯齿波（用键盘选择），信号频率可调（用键盘调节）-the MAX-PLUS design of the consumption function generator, a sine wave, square, triangle area and Sawtooth (keyboard), in signal frequency adjustable (keyboard conditioning)
Platform: | Size: 132905 | Author: 曹海学 | Hits:

[Other resource] 路口交通灯

Description: 个人硬件课程设计，简单实现了FPGA平台的路口交通灯管理，开发环境为MAX+plus-individual hardware curriculum design, a simple realization FPGA platform junction traffic lights management, development environment for MAX plus
Platform: | Size: 118919 | Author: 张宵 | Hits:

[CSharp] pof2jed

Description: MAX+PLUS II 生成pof文件到Atmel15xx系列jed下载格式的转换软件windows版。-MAX PLUS II generation POF documents to the Atmel15xx series jed download format windows version of the software conversion.
Platform: | Size: 1271300 | Author: yibu | Hits:

[Other resource] vhdl-2

Description: UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
Platform: | Size: 59976 | Author: lileiming | Hits:

[Other resource] numberword

Description: 计数器控制程序，希望能够给大家帮助！文件在ＭＡＸ　ＰＬＵＳ下开发，调试通过-counter control procedures, we hope to be able to help! MAX PLUS document under development, through debugging
Platform: | Size: 819 | Author: 吴军 | Hits:

[Other resource] electric_bell

Description: 电子打铃器 在max plus 2 下编译通过-electronic bell playing for the max plus 2 under through compiler
Platform: | Size: 13902 | Author: wenquan | Hits:

[VHDL-FPGA-Verilog] 基于FPGA的李沙育图形发生器

Description: 这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware description language).
Platform: | Size: 791552 | Author: 孔玉 | Hits:

[Books] fpga 和 cpld入门教程

Description: 本教程定位于FPGA/CPLD的快速入门。以ALTERA公司的芯片和相应的开发软件为目标载体进行阐述，本教程阐述了ALTERA主要系列芯片PLD芯片的结构和特点以及相应的开发软件MAX和Plusa和Quartus的使用-position in the handbook FPGA/CPLD Quick Start. With Altera's chips and the corresponding development of software for the target vector elaborate, the tutorials explain the main chips Altera PLD chips on the structure and characteristics of the corresponding software development MA Plusa and X and the use Quartus
Platform: | Size: 4328448 | Author: 小易 | Hits:

[VHDL-FPGA-Verilog] maxshiyan

Description: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
Platform: | Size: 865280 | Author: 田晶昌 | Hits:

[Other] MAXPLUS

Description: Altera公司的max+plus2软件的详细使用演示,从入门到精通-Altera's max plus2 use of the detailed software demonstrations, from entry level to proficiency
Platform: | Size: 262144 | Author: 苏航 | Hits:

[VHDL-FPGA-Verilog] chengxufengxiang

Description: 这些程序我用MAX+PlusII软件测试均能通过编译，程序本身不复杂，旨在为刚接触VHDL语言的朋友提供一些样例，以便了解VHDL语言的基本构成。如果要运行测试，则新建文件名应于程序中实体名一致，文件后缀“.vhd”，不推荐直接通过复制、粘贴的方法录入程序，可能会引入错误字符。 -these procedures I used MAX PlusII Software Testing pass compiler, the process itself is not complicated. for the fourth year to VHDL friend to provide some examples in order to understand the VHDL basic components. If testing, the new file name in the process should be entity line extensions. " Vhd " not recommended directly by copying and pasting the time of admission procedures, the potential introduction of the wrong characters.
Platform: | Size: 1024 | Author: zhaoting | Hits:

[Software Engineering] MAX+plus2

Description: maxplus_2的入门书籍，对刚接触maxplus的朋友很有帮助。希望对大家有所帮助-maxplus_2 entry books,刚接触maxplus of helpful friends. I hope all of you to help
Platform: | Size: 20413440 | Author: 方文利 | Hits:

[VHDL-FPGA-Verilog] myproject

Description: 四位全加器，VHDL语言，max+plusII平台做的-Four full-adder, VHDL language, max+ PlusII platform to do
Platform: | Size: 56320 | Author: 邱飞 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 《VDHL硬件描述语言与数字逻辑》 ——————电子工程师必备知识 西安电子科技大学出版社出版 第一章 数字系统硬件设计概述 第二章 VHDL语言程序的基本结构 第三章 VHDL语言的数据类型及运算操作符 第四章 VHDL语言构造体的描述方式 第五章 VHDL语言的主要描述语言 第六章 数值系统的状态模型 第七章 基本逻辑电路设计 第八章 仿真与逻辑综合 第九章 计时电路设计实例 第十章 微处理器接口芯片设计实例 第十一章 93版和87版VHDL语言的主要区别 第十二章 MAX+plusII使用说明
Platform: | Size: 18693120 | Author: 陈松 | Hits:

[VHDL-FPGA-Verilog] a_block_with_several_functions_with_Verilog_HDL.ra

Description: Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大，应用硬件描述语言进行描述的CPLD结构，成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计，达到对Verilog HDL的理解，同时对CPLD器件进行简要了解。 本文的研究内容包括: 对Altera公司Flex 10K系列的EPF10K 10简要介绍，Altera公司软件Max+plusⅡ简要介绍和应用Verilog HDL对多功能电子钟进行设计。 -Verilog is the most widely used hardware description language.It can be used to the modeling, synthesis, and simulation stages of the hardware system design flow. With the scale of hardware design continually enlarging, describing the CPLD with HDL become the mainstream of designing ASIC and other IC.To comprehend Verilog HDL and get some knowledge of CPLD device, we design a block with several functions with Verilog HDL. This thesis is about to discuss the above there aspects: Introduce the EPF10K 10 of Flex 10K series producted by Altera Corporation simply. the software Max+plusⅡ,Design the block with several functions with Verilog HDL.
Platform: | Size: 482304 | Author: li | Hits:

[Windows Develop] 1

Description: Designing with MAX+PLUS II，可以下载下来，作为了解用-Designing with MAX+ PLUS II, can be downloaded and used as a knowledge
Platform: | Size: 905216 | Author: lz | Hits:

[SCM] MAXplusIICrack

Description: MAX+plus II FPGA CPLD开发软件完美无限制破解版-MAX+ plus II FPGA CPLD development software cracked unlimited version of the perfect
Platform: | Size: 134144 | Author: 吴玉保 | Hits:

[VHDL-FPGA-Verilog] MaxplusII

Description: 本电子书详细地介绍了VHDL语言开发环境 Max+plus II 软件的使用方法，让新手很快学会如何使用本软件-This book describes in detail VHDL language development environment Max+ plus II software to use, so that novices will soon learn how to use the software
Platform: | Size: 1048576 | Author: may | Hits:

[Other] nios

Description: Quartus II为ALTERA公司取代大家所熟悉的最通用工具的MAX+PLUS II软件的升级版本，MAX+PLUS II在2000年已经停止更新了，而Quatrus目前已经更新到6.0版本，里面集成了很多非常有用的工具，如SOPC BUILDER等，这个工具相比其他同类EDA开发工具，和MAX+PLUS II一样仍是最好用的。MAX+PLUS II 用户可以非常方便的转入QUARTUS II工具的使用，因为用户可以选择和MAX+PLUS II一样的操作界面，况且有大量的中文说明可以帮助您更加详细的了解QUARTUS II的使用。-Quartus II for the ALTERA company will replace the familiar of the most common tools of the MAX+ PLUS II software, upgrade, MAX+ PLUS II in 2000, has stopped updating, while Quatrus now updated to version 6.0, which integrates a lot of very useful tools such as SOPC BUILDER etc., this tool compared with other similar development tools, EDA, and the MAX+ PLUS II uses the same is still the best. MAX+ PLUS II users can very easily turn to QUARTUS II the use of tools, because users can select and MAX+ PLUS II the same interface, and since a large number of Chinese explanation can help you more detailed understanding of QUARTUS II use.
Platform: | Size: 2936832 | Author: 蒋思 | Hits:

[VHDL-FPGA-Verilog] max

Description: 这是一个在MAX+plus上面的计数器仿真图，基于FPGA的仿真。-This is a counter above the MAX+ plus simulation map, FPGA-based simulation.
Platform: | Size: 18432 | Author: 王天刚 | Hits:
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